1. Field of the Invention
The present invention relates to a semiconductor device, and, in particular, to a semiconductor device reduced in area of a periphery of a semiconductor element having a super junction structure.
2. Description of the Related Art
As a silicon semiconductor wafer achieving high breakdown voltage and low on-resistance, known is, for example, a wafer structure in which pillar-like p type semiconductor layers and n type semiconductor layers are provided so as to form multiple pn junctions each being vertical to a wafer surface.
When a reverse voltage is applied, high breakdown voltage can be achieved in the pn junctions by selecting dopant concentrations and widths of the p type semiconductor layers and n type semiconductor layers to be desired values. In the following, description will be given of such a structure, which will be referred to as a super junction structure.
In a conventional semiconductor device with a super junction structure, p type semiconductor layers and n type semiconductor layers are alternately arranged not only in an element region but also in a terminal region around the element region, to secure certain breakdown voltage. This technology is described for instance in Japanese Patent Application Publications No. 2006-313892 (FIG. 1 on page 9 thereof) and No. 2003-101022 (FIG. 15 on page 9 thereof)).
As one example of such a conventional semiconductor device, a MOSFET with a super junction structure will be described by referring to FIG. 6.
FIG. 6 is a cross-sectional view around a periphery of the MOSFET. This MOSFET has a super junction structure in which p type semiconductor layers 102 and n type semiconductor layers 105 are alternately arranged on an n+ type semiconductor substrate 101. In addition, an element region E of the MOSFET is provided on a top surface of the super junction structure.
In the element region E, a p type base layer 103 is provided in top surfaces of the pillar-like p type semiconductor layers 102 and n type semiconductor layers 105, and gate electrodes 109 are each provided in the p type base layer 103 with a gate insulating film 108 interposed in between, the gate electrodes 109 being deep enough to penetrate the p type base layer 103. N type source diffusion layers 104 are provided in the surface of the p type base layer 103, and a source electrode 107 is provided on the p type base layer 103 and the n type source diffusion layers 104. In addition, p type contact layers 110 are provided between the p type base layer 103 and the source electrode 107.
In FIG. 6, in a region in which MOSFET is formed, more specifically, for example, a region up to an end portion of the p type base layer 103 is set to be an element region E and a region from a circumference of the element region E up to an end portion of the n+ substrate 101 (chip) is set to be a terminal region T, the p type semiconductor layers 102 and the n type semiconductor layers 105 are arranged up to the terminal region T in order to improve breakdown voltage.
In addition, a field plate electrode 114 is provided on the n type semiconductor layers 105 and p type semiconductor layers 102, with an insulating film 113 interposed in between, in the terminal region T. The field plate electrode 114 is connected to the source electrode 107 or the gate electrodes 109, and has an effect of increasing breakdown voltage in cooperation with a p type RESURF (REduced SURface Field) layer 115 provided in an end portion of the p type base layer 103.
In general, in a depletion layer formed in a junction surface between an n type impurity semiconductor layer and a p type impurity semiconductor layer, an internal electric field in the direction from the n type to the p type is formed. Accordingly, in a case where an end portion of the depletion layer is formed in a curved surface shape having a certain curvature, the internal electric field of the depletion layer concentrates around the curved surface. As the curvature of the curved surface is larger, the concentration of the internal electric field is more intensified. Thus, the curvature in the end portion of the depletion layer is needed to be reduced by expanding the depletion layer in a horizontal direction of the substrate.
In order to achieve a super junction structure formed of p type semiconductor layers and n type semiconductor layers, dopant concentrations of the p type semiconductor layer and the n type semiconductor layer have to be sufficiently increased. Since a depletion layer formed in an end portion of an element region E has an extremely large curvature, needed is a configuration in which the curvature of the depletion layer is reduced in the end portion of the element region or in a terminal region around the element region so that sufficient breakdown voltage is secured.
For example, in FIG. 6, the concentration of the internal electric field is reduced by expanding the depletion layer in the horizontal direction of the substrate (a direction parallel to the substrate surface) by using the p type RESURF layer 115 and the field plate electrode 114. In addition, the p type semiconductor layers 102 and the n type semiconductor layers 105 are also provided in the terminal region T. Thereby, sufficient breakdown voltage is secured.
In the case of FIG. 6, the p type semiconductor layers 102 and the n type semiconductor layers 105 in the terminal region T are affected by a voltage applied to the element region E. Thus, the depletion layer sufficiently spreads in the region close to the element region E while spreads less when it comes closer to an end portion.
Accordingly, in the structure, the depletion layer gradually spreads less as it comes closer to the end portion. Thus, at the same time as reduction in curvature by expanding the depletion layer in the horizontal direction of the substrate, reduction in the concentration of the electric field in the end portion of the depletion layer can be achieved by using a guard ring (RESURF layer) or the like.
In other words, not only in a MOSFET, but also in a semiconductor device with a super junction structure, breakdown voltage is generally secured by proving p type semiconductor regions and n type semiconductor regions in the terminal region. From a viewpoint of securing breakdown voltage, the terminal region larger in width is more desirable.
However, even in a case where an area of the element region E is the same, when a number of p type semiconductor layers and n type semiconductor layers are formed in the terminal region, a chip size becomes larger. For example, when compared with a MOSFET not having a super junction structure, that is, a MOSFET in which an element region is formed in an n type semiconductor layer, the MOSFET with a super junction structure becomes larger in chip size, and a yield of chips per wafer is consequently decreased, even if the area of element region and characteristics are the same as those of the MOSFET not having the super junction structure.
A wafer with a super junction structure tends to be costly because a manufacturing process thereof is complicated. Moreover, the smaller yield of chips per wafer causes a problem of further increasing the manufacturing cost.
By contrast, when an increase of the chip size is suppressed, an area of an element region decreases, which leads to an increase in on-resistance in the case of a MOSFET.